1. Field of the Invention
The present invention relates to a multi-stage signal amplifying circuit in which a differential input signal is differentially amplified in a plurality of differential signal amplifiers serially connected with each other in multi-stage to output a differential output signal, and more particularly to a multi-stage signal amplifying circuit manufactured in a small layout area of an integrated circuit while effectively suppressing a direct-current offset occurring in the differential signal amplifiers arranged in the multi-stage.
2. Description of Related Art
FIG. 5 is a circuit diagram showing the configuration of a conventional multi-stage signal amplifying circuit. In FIG. 5, a reference sign 13 indicates each of a plurality of differential signal amplifiers serially connected with each other in multi-stage. A differential input signal (composed of a voltage signal of a voltage Va(in) and a voltage signal of a voltage Vb(in)) is input to the differential signal amplifier 13 arranged in the first stage to be differentially amplified and to output a differential signal, the differential signal is differentially amplified in each of the differential signal amplifiers 13 arranged after the differential signal amplifier 13 of the first stage, and the differential signal amplified in the differential signal amplifier 13 of the final stage is output as a differential output signal (composed of a voltage signal of a voltage Va(out) and a voltage signal of a voltage Vb(out)).
FIG. 6(a) is an input/output characteristic diagram of the differential signal amplifier 13 arranged in the first stage, and FIG. 6(b) is an input/output characteristic diagram of the differential signal amplifier 13 arranged in the final stage. FIG. 6(a) and FIG. 6(b) shows a problem in the conventional multi-stage signal amplifying circuit.
A reference sign 14 is an X axis indicating an input differential voltage (Va(in)-Vb(in) in FIG. 6(a), Va(n-1)-Vb(n-1) in FIG. 6(b)) of the differential input signal (or the differential signal) applied to the differential signal amplifier 13, a reference sign 15 is an Y axis indicating output voltages (Va(1) and Vb(1) in FIG. 6(a), Va(n) and Vb(n) in FIG. 6(b)) of the differential signal or the differential output signal) output from the differential signal amplifier 13, a reference sign 16 indicates a first voltage amplifying characteristic curve (the voltage Va(1) in FIG. 6(a), the voltage Va(n) in FIG. 6(b)) and a second voltage amplifying characteristic curve (the voltage Vb(1) in FIG. 6(a), the voltage Vb(n) in FIG. 6(b)) in the differential signal amplifier 13, a reference sign 17 indicates a time axis, a reference sign 18 indicates two waveforms of input voltages (Va(in) and Vb(in) in FIG. 6(a), or Va(n-1) and Vb(n-1) in FIG. 6(b)) of the differential signal input to the differential signal amplifier 13, a reference sign 19 indicates a time axis, a reference sign 20 indicates two waveforms of output voltages (Va(1) and Vb(1) in FIG. 6(a), or Va(n) and Vb(n) in FIG. 6(b)) of the differential signal output from the differential signal amplifier 13, a reference sign 21 indicates a cross point of the voltage amplifying characteristic curves 16 of the differential signal amplifier 13, and a reference sign 22 indicates a direct-current component difference (called a direct-current offset voltage) between direct-current component values of the output voltage waveforms 20 of the differential signal output from the differential signal amplifier 13.
As shown in FIG. 6(a) and FIG. 6(b), because a plurality of transistors arranged in each differential signal amplifier 13 have characteristics different from each other, even though the differential signal satisfying the input differential voltage of 0 V (Va(in)=Vb(in), or Va(n-1)=Vb(n-1)) is input to the differential signal amplifier 13 of the first stage (or the final stage), there is a case that voltages Va(1) and vb(1) (or voltages Va(n) and Vb(n)) of the differential signal output from the differential signal amplifier 13 of the first stage (or the final stage) do not agree with each other. Therefore, a direct-current offset voltage, of which a value equals to a difference between the output voltages at the input differential voltage of 0 V, is generated between the output voltage waveforms 20 of the differential signal. Also, a region, in which each of the output voltages linearly changes with respect to the input differential voltage, is called a non-saturated region, and a region, in which each of the output voltages does not linearly change with respect to the input differential voltage, is called a saturation region placed outside the non-saturated region. A range of the input differential voltage corresponding to the non-saturated region is called an input dynamic range, and the input differential voltage within the input dynamic range can be used for a signal amplification.
As shown in FIG. 5, in cases where the plurality of differential signal amplifiers 13 are serially connected with each other in the multi-stage, the direct-current component difference between the output voltage waveforms of the differential signal output from the differential signal amplifier 13 of an I-th stage (I=1, 2, - - - ) is amplified with signal components of the differential signal in each differential signal amplifier 13 of an (I+1)-th stage following the I-th stage. Therefore, as shown in FIG. 6(b), the direct-current component difference extraordinarily increased is input to the differential signal amplifier 13 of the final stage. In cases where the direct-current component difference (or the direct-current offset voltage) approaches the input dynamic range of the differential signal amplifier 13, the differential signal input to the differential signal amplifier 13 is amplified in the saturation region. Therefore, there is a problem that the signal component of the differential signal is not substantially amplified.
To avoid this problem, a technique to solve the problem that the direct-current component difference is extraordinarily increased in a plurality of differential signal amplifiers connected with each other in series not to substantially amplify a differential signal is disclosed in the Published Unexamined Japanese Patent Application No. H6-196947 (1994).
FIG. 7 is a circuit diagram showing the configuration of another conventional multi-stage signal amplifying circuit.
In FIG. 7, a reference sign 23 indicates an amplifying unit in which a plurality of differential signal amplifiers are connected with each other in series, a reference sign 24 indicates a low-pass filter composed of a plurality of resistive elements and a plurality of capacitive elements, and a reference sign 25 indicates a direct-current offset compensating circuit. In this conventional multi-stage signal amplifying circuit, a differential signal input to the amplifying unit 23 is amplified, an output of the amplifying unit 23 is filtered in the low-pass filter 24 to extract a direct-current component difference (or a slowly varying component difference) from the output, the direct-current component difference is amplified at a prescribed amplification factor in the direct-current offset compensating circuit 25, and the amplified direct-current component difference is fed back to an input side of the amplifying circuit 23. Therefore, the amplifying circuit 23 is controlled to compensate the direct-current component difference.
Accordingly, the direct-current component difference existing in the output is adjusted to zero, it is prevented that the direct-current component difference approaches the dynamic range of the amplifying circuit 23, so that a signal component of the differential signal can be amplified.
However, because the conventional multi-stage signal amplifying circuit has the configuration shown in FIG. 7, the output of the amplifying circuit 23 is, at first, filtered in the low-pass filter 24, so that it is required that an input impedance of the low-pass filter 24 is heightened. In this case, it is required that values of the resistive elements of the low-pass filter 24 are heightened, so that a size of each resistive element is enlarged. Therefore, there is another problem that a layout area required for the resistive elements of the low-pass filter 24 is considerably increased in cases where the conventional multi-stage signal amplifying circuit is manufactured on a semiconductor substrate.